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automotive power data sheet rev. 1.1, 2014-10-08 tle8250gvio high speed can-transceiver
data sheet 2 rev. 1.1, 2014-10-08 tle8250gvio 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 high speed can physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 normal operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 fail safe functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 open logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 txd time-out function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 functional device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2 output characteristics of the rxd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.3 further application informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table of contents
pg-dso-8 type package marking tle8250gvio pg-dso-8 8250gvio data sheet 3 rev. 1.1, 2014-10-08 high speed can-transceiver tle8250gvio 1overview features ? fully compatible to iso 11898-2 ? wide common mode range for el ectromagnetic immunity (emi) ? very low electromagnetic emission (eme) ? excellent esd robustness ? extended supply range at v cc and v io ? suitable for 5v and 3.3v microcontroller i/o voltages ? can short-circuit proof to ground, battery and v cc ? txd time-out function ? low can bus leakage current in power down mode ? over temperature protection ? protected against automotive transients ? can data transmission rate up to 1 mbit/s ? v io input for voltage adaption to the micro controller supply ? green product (rohs compliant) ? aec qualified description the tle8250gvio is a transceiver designed for can network s in automotive and industrial applications. as an interface between the physical bus layer and the can prot ocol controller, the tle8250gvio drives the signals to the bus and protects the microcontroller against distur bances coming from the network. based on the high symmetry of the canh and canl signals, the tle8250g vio provides a very low level of electromagnetic emission (eme) within a broad frequency range. the tle8 250gvio is integrated in a rohs complaint pg-dso-8 package and fulfills or exceeds the requirements of the iso11898-2. as a successor to the first generation of hs can tr ansceivers, the tle8250gvio is fully pin and function compatible to his predecessor model, the tle6250gv33. the tle8250gvio is optimized to provide an excellent passive behavior in power down mode. this feature makes the tle8250gvio extremely suitable for mixed supply can networks. based on the infineon smart power technology spt ? , the tle8250gvio provides industry leading esd robustness together with a very high electromagnetic immunity (emi). the infineon smart power technology spt ? allows bipolar and cmos control circuitry in acco rdance with dmos power devices to exist on the same monolithic circuit. the tle8250gvio and the infineon spt ? technology are aec qualified and tailored to withstand the harsh conditions of the automotive environment. two different operation modes, additional fail safe feat ures like a txd time-out and the optimized output slew rates on the canh and canl signals are making the tle8250gvio the ideal choice for large can networks with high data rates.
data sheet 4 rev. 1.1, 2014-10-08 tle8250gvio block diagram 2 block diagram figure 1 block diagram note: in comparison to the tle6250gv33 the pin 8 (inh) was renamed to the term ne n, the function remains unchanged. nen stands for not enable. receiver output stage driver temp- protection mode control * = 7 canh 6 canl 2 gnd txd 1 3 v cc nen 8 v io 5 rxd 4 timeout output driver stage receive unit v cc /2
tle8250gvio pin configuration data sheet 5 rev. 1.1, 2014-10-08 3 pin configuration 3.1 pin assignment figure 2 pin configuration 3.2 pin definitions and functions table 1 pin definition and functions pin symbol function 1txd transmit data input; internal pull-up to v io , ?low? for ?dominant? state. 2gnd ground 3 v cc transceiver supply voltage; 100 nf decoupling capacitor to gnd required. 4rxd receive data output; ?low? in ?dominant? state. 5 v io digital supply voltage input; supply voltage input to adapt the logical input and output voltage levels of the transceiver to the microcontroller supply. 100 nf decoupling capacitor to gnd required. 6canl can bus low level i/o; ?low ? in ?dominant? state. 7canh can bus high level i/o; ?high? sin ?dominant? state. 8nen not enable input 1) ; internal pull-up to v io , ?low? for normal operation mode. 1) the naming of pin 8 is different betw een the tle8250gvio and its forerunner m odel the tle6250gv33. the function of pin 8 remains the same. txd 1 2 3 45 6 7 8 rxd nen gnd v cc canh canl v io
data sheet 6 rev. 1.1, 2014-10-08 tle8250gvio functional description 4 functional description can is a serial bus system that connects microcontrollers , sensor and actuators for real-time control applications. the usage of the c ontrol a rea n etwork (abbreviated can) within road vehi cles is described by the international standard iso 11898. according to the 7 layer osi reference model the physical layer of a can bus system specifies the data transmission from one can node to a ll other available can nodes inside the network. the physical layer specification of a can bus system includes all electrical and mechanical specifications of a can network. the can transceiver is part of the physical laye r specification. several diffe rent physical layer standards of can networks have been developed over the last ye ars. the tle8250gvio is a high speed can transceiver without any dedicated wake-up function. high speed ca n transceivers without wake-up function are defined by the international standard iso 11898-2. 4.1 high speed c an physical layer figure 3 high speed can bus signals and logic signals v cc can_h can_l txd v io = logic power supply v cc = can power supply txd = input from the microcontroller rxd = output to the microcontroller canh = voltage on the canh input/output canl = voltage on the canl input/output v diff = differential voltage between canh and canl v diff = v canh C v canl rxd v diff dominant recessive v io v io t t t t v diff = iso level dominant v diff = iso level recessive
tle8250gvio functional description data sheet 7 rev. 1.1, 2014-10-08 the tle8250gvio is a high speed can transceiver, oper ating as an interface between the can controller and the physical bus medium. a hs can network is a two wire, differential network which allows data transmission rates up to 1 mbit/s. characteristic for a hs can networ k are the two signal states on the can bus: ?dominant? and ?recessive? (see figure 3 ). the pins canh and canl are the interface to the can bus and both pins operate as a input and as an output. the pins rxd and txd are the interface to the microcontro ller. the pin txd is the serial data input from the can controller, the pin rxd is th e serial data output to the can controller. as shown in figure 1 , the hs can transceiver tle8250gvio has a receive and a transmit un it, allowing the transceiver to send data to the bus medium and monitor the data from the bus medium at the same time. the hs can transceiver tle8250gvio converts the serial data stream available on the transmit data input txd, into a differential output signal on can bus, provided by the pins canh and canl. the rece iver stage of the tle8250gvio monitors the data on the can bus and converts them to a serial, single ended signal on the rxd output pin. a logical ?low? signal on the txd pin creates a ?dominant? signal on the can bus, followed by a logical ?low? signal on the rxd pin (see figure 3 ). the feature, broadcasting data to the can bus and listening to the data traffic on the can bus simultaneous is essential to support the bi t to bit arbitration inside can networks. the voltage levels for hs can transceivers are defined by the iso 11898-2 and the iso 11898-5 standards. if a data bit is ?dominant? or ?recessive? depends on the voltage difference between pins canh and canl: v diff = v canh - v canl . in comparison to other differential ne twork protocols the differential signal on a can network can only be larger or equal to 0 v. to transmit a ?dominant? sig nal to the can bus the differential signal v diff is larger or equal to 1.5 v. to receive a ?recessive? signal from the can bus the differential v diff is smaller or equal to 0.5 v. partially supplied can networks are networks where the can bus participants have different power supply conditions. some nodes are connected to the power supp ly, some other nodes are disconnected from the power supply. regardless, if the can bus par ticipant is supplied or not supplied, each participant connected to the common bus media must not disturb the communication . the tle8250gvio is designed to support partially supplied networks. in power down mode, the receiver input resistors are switched off and the transceiver input is high resistive. the voltage level on the digital input txd and the digital ou tput rxd is determined by the power supply level at the pin v io . depending on volt age level at the v io pin, the signal levels on the logic pins (nen, txd and rxd) are compatible to microcontrollers with 5 v or 3.3 v i/o supply. usually the v io power supply of the transceiver is connected to same power supply as i/o power supply of the microcontroller.
data sheet 8 rev. 1.1, 2014-10-08 tle8250gvio functional description 4.2 operation modes two different operation modes are available on tle8250g vio. each mode with specific characteristics in terms of quiescent current or data transmission. for the mode selection the digital input pin nen is used. figure 4 illustrates the differ ent mode changes de pending on the status of th e nen pin. after suppling v cc and v io to the hs can transceiver, the tle8250gvio starts in stand-by mode. the internal pull-up resistor is setting the tle8250gvio to stand-by per default. if the microcont roller is up and running the tle8250gvio can change to operation mode within the time for mode change t mode . figure 4 operation modes the tle8250gvio has 2 major operation modes: ? stand-by mode ? normal operation mode table 2 operating modes mode nen bus bias comments normal operation ?low? v cc /2 output driver stage is active. receiver unit is active. stand-by ?high? floating output driver stage is disabled. receiver unit is disabled. v cc off ?low? or ?high? floating output driver stage is disabled. receiver unit is disabled. undervoltage detection on v cc and v io power down v cc < v cc(uv) start C up supply v cc and v io v io < v io(uv) nen = 0 normal operation mode nen = 1 stand-by mode nen = 0 nen = 1
tle8250gvio functional description data sheet 9 rev. 1.1, 2014-10-08 4.3 normal operation mode in normal operation mode the hs can transceiver tle8250 gvio sends the serial data stream on the txd pin to the can bus while at the same time the data availabl e on the can bus are monitored to the rxd pin. in normal operation mode all functions of the tle8250gvio are active: ? the output driver stage is active and drives data from the txd to the can bus. ? the receiver unit is active and provides the data from the can bus to the rxd pin. ? the bus basing is set to v cc /2. ? the under-voltage monitoring on the power supply v cc and on the power supply v io is active. to enter the normal operation mode set the pin nen to logical ?low? (see table 2 or figure 4 ). the nen pin has an internal pull-up resistors to the power-supply v io . 4.4 stand-by mode stand-by mode is an idle mode of the tle8250gvio with optimized power consumption. in stand-by mode the tle8250gvio can not send or receive any data. the output driver stage and the normal receiver unit are disabled. both can bus pins, canh and canl are floating. ? the output driver stage is disabled. ? the receiver unit is disabled. ? the bus basing is floating. ? the under-voltage monitoring on the power supply v cc and on the power supply v io is active. to enter the stand-by mode set the pin nen to logical ?high? (see table 2 or figure 4 ). the nen pin has an internal pull-up resistor to the power-supply v io . in case the stand-by mode will not be used in the application, the nen pin needs to get connected to gnd. 4.5 power down power down mode means the tle8250gvio is not supplied. in power down the differential input resistors of the receiver stage are switched off. the canh and canl bus interface of the tle8250gvio acts as an high impedance input with a very small leakage current. the hi gh ohmic input doesn?t influence the ?recessive? level of the can network and allows an optimize d eme performance of the whole can network.
data sheet 10 rev. 1.1, 2014-10-08 tle8250gvio fail safe functions 5 fail safe functions 5.1 short circuit protection the canh and canl bus outputs are short-circuit-proof, either against gnd or a positive supply voltage. a current limiting circuit protects the tran sceiver against damages. if the device is heating up due to a continuos short on canh or canl, the internal over-temperature protection switches off the bus transmitter. 5.2 open logic pins all logic input pins have internal pull-up resistor to v io . in case the v io supply is activated and the logical pins are open or floating, the tle8250gvio enters into the stand-by mode per default. in stand-by mode the output driver stage of the tle8250gvio is disabled, the bus biasing is shut off and t he hs can tle8250gvio transceiver will not influence the data on the can bus. 5.3 txd time-out function the txd time-out feature protects the can bus against permanent blocking in case the logical signal on the txd pin is continuously ?low?. a conti nuous ?low? signal on the txd pin can have it?s root cause in a locked-up microcontroller or a short on the printed circuit board for example. in normal operation mode, a logical ?low? signal on the txd pin for the time t > t txd enables the txd time-out feature and the tle8250gvio disables the output driver stage (see figure 5 ). the receive unit is still active and th e data on the bus are still monitored by the rxd output pin. figure 5 txd time-out function figure 5 shows the way how the transmission stage is deacti vated and activated again. a permanent ?low? signal on the txd input pin activates the txd time-out function an d deactivates the transmitter output stage. to release the transmitter output stage after a txd time-out event th e tle8250gvio requires a signal change on the txd input pin from logical ?l ow? to logical ?high?. txd t t canh canl rxd t txd time - out txd time C out released t > t txd
tle8250gvio fail safe functions data sheet 11 rev. 1.1, 2014-10-08 5.4 under-voltage detection the hs can transceiver tle8250gvio is equipped wi th an under-voltage detection on the power supply v cc and the power supply v io . in case of an under-voltage event on v cc or v io , the under-voltage detection changes the operation mode of tle8250gvio to the stand-by mode, regardless to the logical signal on the nen pin (see figure 6 ).if the transceiver tle8250gvio recovers from th e under-voltage event, the operation mode returns to the programmed mode by the nen pin. figure 6 under-voltage detection on v cc and v io supply voltage v cc power down reset level v cc(uv) normal operation mode stand-by mode normal operation mode 1) nen = 0 nrm = 1 1) assuming the logical signal on the pin nen keeps its values during the under- voltage event. in this case nen remains ?low. supply voltage v io power down reset level v io(uv) blanking time t blank,uv time for mode change t mode normal operation mode stand-by mode normal operation mode 1) nen = 0 nrm = 1 blanking time t blank,uv time for mode change t mode
data sheet 12 rev. 1.1, 2014-10-08 tle8250gvio fail safe functions 5.5 over-temperature protection figure 7 over-temperature protection the tle8250gvio has an integrated over-temperature de tection to protect the device against thermal overstress of the output driver stage. in case of an ov er-temperature event, the temperature sensor will disable the output driver stage (see figure 1 ). after the device cools down the output driver stage is ac tivated again (see figure 7 ). inside the temperature sensor a hysteresis is implemented. txd t t canh canl rxd t overtemperature event cool down t j t t jsd (shut down temperature) t jso (switch on temperature)
tle8250gvio general product characteristics data sheet 13 rev. 1.1, 2014-10-08 6 general product characteristics 6.1 absolute maximum ratings note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. table 3 absolute maximum ratings voltages, currents and temperatures 1) a ll voltages with respect to ground; positive current flowing into pin; (unless otherwise specified) pos. parameter symbol limit values unit remarks min. max. voltages 6.1.1 transceiver supply voltage v cc -0.3 6.0 v ? 6.1.2 logic supply voltage v io -0.3 6.0 v ? 6.1.3 canh dc voltage versus gnd v canh -40 40 v ? 6.1.4 canl dc voltage versus gnd v canl -40 40 v ? 6.1.5 differential voltage between canh and canl v can diff -40 40 v 6.1.6 logic voltages at nen, txd, rxd v i -0.3 6.0 v ? temperatures 6.1.7 junction temperature t j -40 150 c? 6.1.8 storage temperature t s - 55 150 c? esd resistivity 6.1.9 esd resistivity at canh, canl versus gnd v esd -8 8 kv human body model (100pf via 1.5 k ) 2) 6.1.10 esd resistivity all other pins v esd -2 2 kv human body model (100pf via 1.5 k ) 2) 1) not subject to production test, specified by design 2) esd susceptibility hbm accord ing to eia / jesd 22-a 114
data sheet 14 rev. 1.1, 2014-10-08 tle8250gvio general product characteristics 6.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 6.3 thermal characteristics note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . table 4 operating range pos. parameter symbol limit values unit conditions min. max. supply voltages 6.2.1 transceiver supply voltage v cc 4.5 5.5 v ? 6.2.2 logical supply voltage v io 3.0 5.5 v ? thermal parameters 6.2.3 junction temperature t j -40 150 c 1) 1) not subject to production test, specified by design table 5 thermal resistance 1) 1) not subject to production test, specified by design pos. parameter symbol limit values unit remarks min. typ. max. thermal resistance 6.3.1 junction to ambient 1) r thja ?130?k/w 2) 2) specified r thja value is according to jedec jesd51-2,-7 at natural convection on fr4 2s2p board; the product (tle8250gvio) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). thermal shutdown junction temperature 6.3.2 thermal shutdown temp. t jsd 150 175 200 c ? 6.3.3 thermal shutdown hysteresis t10k?
tle8250gvio electrical characteristics data sheet 15 rev. 1.1, 2014-10-08 7 electrical characteristics 7.1 functional device characteristics table 6 electrical characteristics 4.5 v < v cc <5.5v; 3.0v< v io <5.5v; r l =60 ; -40c < t j < +150c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limi t values unit remarks min. typ. max. current consumption 7.1.1 current consumption on v cc i cc ? 6 10 ma ?recessive? state; v txd = v io 7.1.2 current consumption on v cc i cc ? 45 70 ma ?dominant? state; v txd = 0 v 7.1.3 current consumption i cc(stb) ?7 15 a stand-by mode; txd = v io , nen = ?low? 7.1.4 current consumption i io ? ? 1 ma normal operation mode nen = ?low? supply resets 7.1.5 v cc under-voltage monitor v cc(uv) 1.3 3.2 4.3 v ? 7.1.6 v cc under-voltage monitor hysteresis v cc(uv,h) ? 200 ? mv 1) 7.1.7 v io under-voltage monitor v io(uv) 1.3 2.4 2.8 v ? 7.1.8 v io under-voltage monitor hysteresis v io(uv,h) ? 200 ? mv 1) 7.1.9 v cc and v io under-voltage blanking time t blank(uv) ?15? s 1) receiver output: rxd 7.1.10 high level output current i rd,h ?-4-2ma v rxd = 0.8 v io v diff < 0.5 v 7.1.11 low level output current i rd,l 24 ?ma v rxd = 0.2 v io v diff > 0.9 v transmission input: txd 7.1.12 high level input voltage threshold v td,h ?0.5 v io 0.7 v io v ?recessive? state 7.1.13 low level input voltage threshold v td,l 0.3 v io 0.4 v io ? v ?dominant? state 7.1.14 txd pull-up resistance r td 10 25 50 k ? 7.1.15 txd input hysteresis v hys(txd) ? 200 ? mv 1) 7.1.16 txd permanent dominant disable time t txd 0.3 ? 1.0 ms ?
data sheet 16 rev. 1.1, 2014-10-08 tle8250gvio electrical characteristics not enable input nen 7.1.17 high level input voltage threshold v nen,h ?0.5 v io 0.7 v io v stand-by mode; 7.1.18 low level input voltage threshold v nen,l 0.3 v io 0.4 v io ? v normal operation mode; 7.1.19 nen pull-up resistance r nen 10 25 50 k ? 7.1.20 nen input hysteresis v hys(nen) ? 200 ? mv 1) bus receiver 7.1.21 differential receiver threshold ?dominant? v diff,(d) ? 0.75 0.9 v normal operation mode 7.1.22 differential receiver threshold ?recessive? v diff,(r) 0.5 0.6 ? normal operation mode 7.1.23 differential receiver input range - ?dominant? v diff,rdn 0.9 ? 5.0 v normal operation mode 7.1.24 differential receiver input range - ?recessive? v diff,drn -1.0 ? 0.5 v normal operation mode 7.1.25 common mode range cmr -12 ? 12 v v cc = 5 v 7.1.26 differential receiver hysteresis v diff,hys ? 100 ? mv 1) 7.1.27 canh, canl input resistance r i 10 20 30 k ?recessive? state 7.1.28 differential input resistance r diff 20 40 60 k ?recessive? state 7.1.29 input resistance deviation between canh and canl r i -3 ? 3 % 1) ?recessive? state 7.1.30 input capacitance canh, canl versus gnd c in ?2040pf 1) v txd = v cc 7.1.31 differential input capacitance c indiff ?1020pf 1) v txd = v cc bus transmitter 7.1.32 canl/canh recessive output voltage v canl/h 2.0 2.5 3.0 v v txd = v io; no load 7.1.33 canh, canl recessive output voltage difference v diff -500 ? 50 mv v txd = v io ; no load 7.1.34 canl dominant output voltage v canl 0.5 ? 2.25 v 4.75 v < v cc <5.25v, v txd = 0 v, 50 < r l <65 ; 7.1.35 canh dominant output voltage v canh 2.75 ? 4.5 v 4.75 v < v cc <5.25v, v txd = 0 v, 50 < r l <65 ; 7.1.36 canh, canl dominant output voltage difference v diff = v canh - v canl v diff 1.5 ? 3.0 v 4.75 v < v cc <5.25v, v txd = 0 v, 50 < r l <65 ; 7.1.37 driver symmetry v sym = v canh + v canl v sym 4.5 ? 5.5 v v txd = ?low?; v cc = 5 v 50 < r l <65 table 6 electrical characteristics (cont?d) 4.5 v < v cc <5.5v; 3.0v< v io <5.5v; r l =60 ; -40c < t j < +150c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limi t values unit remarks min. typ. max.
tle8250gvio electrical characteristics data sheet 17 rev. 1.1, 2014-10-08 7.1.38 canl short circuit current i canlsc 50 100 200 ma v canlshort = 18 v 7.1.39 canh short circuit current i canhsc -200 -100 -50 ma v canhshort = 0 v 7.1.40 leakage current i canhl,lk -5 0 5 a v cc =0v; v canh = v canl ; 0v< v canh,l <5v table 6 electrical characteristics (cont?d) 4.5 v < v cc <5.5v; 3.0v< v io <5.5v; r l =60 ; -40c < t j < +150c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limi t values unit remarks min. typ. max.
data sheet 18 rev. 1.1, 2014-10-08 tle8250gvio electrical characteristics 7.2 diagrams figure 8 simplified test circuit dynamic can-transceiver characteristics 7.1.41 propagation delay txd-to-rxd low (?recessive? to ?dominant?) t d(l),tr ?? 255ns c l = 100 pf; v cc =5v; c rxd =15pf 7.1.42 propagation delay txd-to-rxd high (?dominant? to ?recessive?) t d(h),tr ?? 255ns c l = 100 pf; v cc =5v; c rxd =15pf 7.1.43 propagation delay txd low to bus ?dominant? t d(l),t ? 110 ? ns c l = 100 pf; v cc =5v; c rxd =15pf 7.1.44 propagation delay txd high to bus ?recessive? t d(h),t ? 110 ? ns c l = 100 pf; v cc =5v; c rxd =15pf 7.1.45 propagation delay bus ?dominant? to rxd ?low? t d(l),r ?70?ns c l = 100 pf; v cc =5v; c rxd =15pf 7.1.46 propagation delay bus ?recessive? to rxd ?high? t d(h),r ? 100 ? ns c l = 100 pf; v cc =5v; c rxd =15pf 7.1.47 time for mode change t mode ?? 10 s 1) 1) not subject to production test, specified by design table 6 electrical characteristics (cont?d) 4.5 v < v cc <5.5v; 3.0v< v io <5.5v; r l =60 ; -40c < t j < +150c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limi t values unit remarks min. typ. max. 3 gnd 2 4 5 1 8 100 nf 6 canl 7 canh r l v cc v io txd nen rxd c l c rxd 100 nf
tle8250gvio electrical characteristics data sheet 19 rev. 1.1, 2014-10-08 figure 9 timing diagram for dynamic characteristics t d(l),r t v diff t d(l),tr t d(h),r t d(h),tr t d(l),t t gnd v txd v io t d(h),t 0,9v t gnd 0.2 x v io 0.8 x v io v rxd v io 0,5v
data sheet 20 rev. 1.1, 2014-10-08 tle8250gvio application information 8 application information 8.1 application example figure 10 simplified application for the tle8250gvio example ecu design v bat a tle8250gvio v cc canh canl gnd nen txd rxd 7 6 1 4 8 2 3 microcontroller e.g. xc22xx v cc gnd out out in tle4476d gnd iq1 100 nf 100 nf 22 uf optional: common mode choke en q2 v io 22 uf 100 nf tle8250gvio v cc canh canl gnd nen txd rxd 7 6 1 4 8 2 3 microcontroller e.g. xc22xx v cc gnd out out in tle4476d gnd iq1 100 nf 100 nf 22 uf optional: common mode choke en q2 v io 22 uf 100 nf 5 5 canh canl canh canl 120 ohm 120 ohm
tle8250gvio application information data sheet 21 rev. 1.1, 2014-10-08 8.2 output characteris tics of the rxd pin the rxd output pin is designed as a push-pull output stage (see figure 1 ), meaning to produce a logical ?low? signal the tle8250gvio switches the rxd output to gnd. vice versa to produce a logical ?high? signal the tle8250gvio switches the rxd output to v io . the level v rxd,h for a logical ?high? signal on the rxd outpu t depends on the load at the rxd output pin and therefore on the rxd output current i rd,h . the voltage level v rxd,h also depends on the voltage of the power supply v io . according to the operating range (see table 4 ) the power supply v io can vary between 3.0 v and 5.5 v. at a v io supply of 5 v the output current of the rxd pi n on the tle8250gvio is higher as in comparison for a v io supply of 3.3 v. for a load against the gnd potential, the current i rd,h is flowing out of the rxd output pin. similar to the logical ? high? signal, the level v rxd,l for a logical ?low? signal on the rxd output pin depends on the input current i rd,l and the power supply voltage v io . for a load against the power supply v io the current i rd,l is flowing into the rxd output pin. currents flowing into the device are marked positive inside the data sheet and currents flowing out of the device tle8250gvio are marked negative inside the data sheet (see table 6 ). the diagram in figure 11 shows the output current capability of the rxd output pin depended on the chip temperature t j at a v io power supply of 5.0 v. figure 12 shows the output current ca pability of the rxd output pin at a v io power supply of 3.3 v. both diagrams show the output current for a logical ?high? level v rxd,h = 4.6 v. the can transceiver tle8250gvio provides a logical ?high? signal on the rxd output while the signal on the can bus is ?recessive? (see figure 3 ): ? the curve ? v rxd,h = 4.6 v; typ. output current; v cc =5.0v; v io =5.0 v;? displays the typical output current at the rxd output pin of the tle8250gvio (see figure 11 ). for this graph v cc = 5.0 v and v io =5.0v. ?the curve ? v rxd,h = 4.6 v; typ. output current + 6 sigma; v cc =5.0v; v io =5.0 v;? displays the expected maximum value of the output current at the rxd output pin (see figure 11 ). for this graph v cc = 5.0 v and v io =5.0v. ?the curve ? v rxd,h = 4.6 v; typ. output current - 6 sigma; v cc =5.0v; v io =5.0 v;? displays the expected minimum value of the output current at the rxd output pin (see figure 11 ). for this graph v cc = 5.0 v and v io =5.0v. ? the curve ? v rxd,h = 4.6 v; typ. output current; v cc =5.0v; v io =3.3 v;? displays the typical output current at the rxd output pin of the tle8250gvio (see figure 12 ). for this graph v cc = 5.0 v and v io =3.3v. ?the curve ? v rxd,h = 4.6 v; typ. output current + 6 sigma; v cc =5.0v; v io =3.3 v;? displays the expected maximum value of the output current at the rxd output pin (see figure 12 ). for this graph v cc = 5.0 v and v io =3.3v. ?the curve ? v rxd,h = 4.6 v; typ. output current - 6 sigma; v cc =5.0v; v io =3.3 v;? displays the expected minimum value of the output current at the rxd output pin (see figure 12 ). for this graph v cc = 5.0 v and v io =3.3v. the diagram in figure 13 and the diagram in figure 14 show the current capabilit y of the rxd output pin depended on the chip temperature t j . figure 13 shows the current capability of the rxd output pin at a v io power supply of 5.0 v and figure 14 shows the current capability of the rxd output pin at a v io power supply of 3.3 v. both diagrams show the output current for a logical ?low? level v rxd,h = 0.4 v. the can transceiver tle8250gvio provides a logical ?low? signal on the rxd output while the signal on the can bus is ?dominant? (see figure 3 ): ? the curve ? v rxd,h = 0.4 v; typ. output current; v cc =5.0v; v io =5.0 v;? displays the typical output current at the rxd output pin of the tle8250gvio (see figure 13 ). for this graph v cc = 5.0 v and v io =5.0v.
data sheet 22 rev. 1.1, 2014-10-08 tle8250gvio application information ?the curve ? v rxd,h = 0.4 v; typ. output current + 6 sigma; v cc =5.0v; v io =5.0 v;? displays the expected maximum value of the output current at the rxd output pin (see figure 13 ). for this graph v cc = 5.0 v and v io =5.0v. ?the curve ? v rxd,h = 0.4 v; typ. output current - 6 sigma; v cc =5.0v; v io =5.0 v;? displays the expected minimum value of the output current at the rxd output pin (see figure 13 ). for this graph v cc = 5.0 v and v io =5.0v. ? the curve ? v rxd,h = 0.4 v; typ. output current; v cc =5.0v; v io =3.3 v;? displays the typical output current at the rxd output pin of the tle8250gvio (see figure 14 ). for this graph v cc = 5.0 v and v io =3.3v. ?the curve ? v rxd,h = 0.4 v; typ. output current + 6 sigma; v cc =5.0v; v io =3.3 v;? displays the expected maximum value of the output current at the rxd output pin (see figure 14 ). for this graph v cc = 5.0 v and v io =3.3v. ?the curve ? v rxd,h = 0.4 v; typ. output current - 6 sigma; v cc =5.0v; v io =3.3 v;? displays the expected minimum value of the output current at the rxd output pin (see figure 14 ). for this graph v cc = 5.0 v and v io =3.3v.
tle8250gvio application information data sheet 23 rev. 1.1, 2014-10-08 figure 11 rxd output driver capabi lity for a logical ?high? signal v rxd,h =4.6 v, v cc =5.0 v, v io =5.0 v 1) figure 12 rxd output driver capabi lity for a logical ?high? signal v rxd,h =4.6 v, v cc =5.0 v, v io =3.3 v 1) 1) characteristics generated by simulation and specified by design. production test criteria is described in table 6 ; pos.: 7.1.10
data sheet 24 rev. 1.1, 2014-10-08 tle8250gvio application information figure 13 rxd output driver capa bility for a logical ?low? signal v rxd,h =0.4 v, v cc =5.0 v, v io =5.0 v 1) figure 14 rxd output driver capa bility for a logical ?low? signal v rxd,h =0.4 v, v cc =5.0 v, v io =3.3 v 1) 1) characteristics generated by simulation and specified by design. production test criteria is described in table 6 ; pos.: 7.1.11
tle8250gvio application information data sheet 25 rev. 1.1, 2014-10-08 8.3 further application information ? please contact us for information regarding the fmea pin. ? existing app. note (title) ? for further information you may contact http://www.infineon.com/transceiver
data sheet 26 rev. 1.1, 2014-10-08 tle8250gvio package outlines 9 package outlines figure 15 pg-dso-8 (plastic dual small outline pg-dso-8-16) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). +0.06 0.19 0.35 x 45? 1) -0.2 4 c 8 max. 0.64 0.2 6 0.25 0.2 8x m c 1.27 +0.1 0.41 0.2 m a -0.06 1.75 max. (1.45) 0.07 0.175 b 8x b 2) index marking 5 -0.2 1) 4 1 85 a 1) does not include plastic or metal protrusion of 0.15 max. per side 2) lead width can be 0.61 max. in dambar area gps01181 0.1 for further information on alternativ e packages, please vi sit our website: http://www.infineon.com/packages . dimensions in mm
tle8250gvio revision history data sheet 27 rev. 1.1, 2014-10-08 10 revision history revision date changes 1.1 2014-9-26 update from data sheet rev. 1.00: ? all pages: revision and date updated. spelling and grammar corrected. ? cover page: logo and layout updated. ? page 3 , overview: feature list updated (?extended supply range at v cc and v io ?). ? page 14 , table 4 , parameter 6.2.1 : supply range updated (?4.5 v < v cc <5.5v?). ? page 14 , table 4 , parameter 6.2.2 : supply range updated (?3.0 v < v io <5.5v?). ? page 15 , table 6 : table header updated (?4.5 v < v cc <5.5v?). table header updated (?3.0 v < v io <5.5v?). ? page 16 , table 6 , parameter 7.1.29 : new parameter added. ? page 16 , table 6 , parameter 7.1.30 : new parameter added. ? page 16 , table 6 , parameter 7.1.31 : new parameter added. ? page 16 , table 6 , parameter 7.1.34 : remark added (?4.75 v < v cc < 5.25v?). ? page 16 , table 6 , parameter 7.1.35 : remark added (?4.75 v < v cc < 5.25v?). ? page 16 , table 6 , parameter 7.1.36 : remark added (?4.75 v < v cc < 5.25v?). ? page 20 , figure 10 : picture updated. ? page 21 , chapter 8.2 : description updated, renamed the term typical input current to typical output current. ? page 23 ff, figure 11 , figure 12 , figure 13 , figure 14 : picture updated ? page 27 : revision history updated 1.0 2010-09-02 data sheet created
edition 2014-10-08 published by infineon technologies ag 81726 munich, germany ? 2006 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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